The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to device structures for a fin-type field-effect transistor (FinFET) and methods for fabricating a device structure for a FinFET.
A FinFET is a non-planar device structure that is capable of being more densely packed in an integrated circuit than planar field-effect transistors. In addition to the increase in packing density, FinFETs also offer superior short channel scalability, reduced threshold voltage swing, higher mobility, and the ability to operate at lower supply voltages than traditional planar field-effect transistors. A FinFET includes one or more fins of semiconductor material and an overlapping gate electrode that intersects a channel of the one or more fins. The fin dimensions determine the effective channel width of the FinFET. Heavily-doped source/drain regions are formed in fin sections that are not covered by the gate electrode. The channel is located in each fin between these heavily-doped source/drain regions.
A super steep retrograde well (SSRW) may be formed below each fin in an underlying bulk substrate. The SSRW may be employed to improve drain induced barrier lowering (DIBL) and to prevent punchthrough at the bottom of each fin. The SSRW may also mitigate dopant diffusion into the fin, which can result in varying threshold voltage along a fin height and can also result in random dopant fluctuations.
Improved device structures for a FinFET and fabrication methods for making such device structures for a FinFET are needed.